UROP Proceedings 2022-23

School of Engineering Department of Electronic and Computer Engineering 148 Video Compression via Deep Learning for Resource-constrained Edge AI Systems Supervisor: ZHANG, Jun / ECE Student: ZHANG, Yutian / CPEG Course: UROP3100, Fall In recent years, deep learning has dominated the field of computer vision, e.g., image recognition, superresolution, etc. Given its powerful ability in modeling complex data distributions, recently it also entered the field of image and video compression. Thanks to intensive research in past years, deep learning-based compression methods have greatly improved the efficiency and accuracy over traditional compression algorithms. This paper will first briefly introduce critical components of image and video compression and then focus on an example of deep-learning base algorithms for image compression. Extensive comparisons will be provided against traditional algorithms, including JPEG and WebP. Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG, Yihan / ECE Student: GU, Liming / SENG Course: UROP1000, Summer The goal of the project is to design an electronic lock and have it fabricated on silicon (or, taped-out) as a piece of integrated circuit (IC) chip using a tapeout service provided by tinytapeout.com. The project includes two phases, the designing phase and the verification phase. During the design phase, we will build the electronic lock in Verilog. Simulation will be carried out to ensure proper functionality and corresponding data will be prepared in accordance with the tapeout requirement. In the verification phase, we will test the functionality of the physical chip using real-world equipment after it is fabricated and returned. The report will describe the progress that we have made. It includes digital circuit basics and Verilog HDL syntax, which are essential knowledge and skills to realize the proposed design. The report will also introduce what we will do in the future, including the rest of the process to submit our work to TinyTapeout, as well as other design ideas that can be realized using the same workflow. Open-Source Digital Integrated Circuit Design and Tapeout Supervisor: ZHANG, Yihan / ECE Student: LIM, Kiheon / SENG Course: UROP1000, Summer The purpose of the UROP project is to design a piece of digital integrated circuit through open source tapeout (a process to translate IC in computer data to a real piece of silicon), including conceptualization, design, debugging, and verification. Through this process, we will develop expertise in Verilog coding, digital integrated circuit design, tapeout flow, and circuit. Here, a Smart Home Energy Management system is proposed, where it utilizes the experience and knowledge on Verilog coding and tapeout, acquired through the fundamental stages and expertise of the project. The report highlights the potential steps following up the learning process, where further research and actual execution of coding, synthesis, and optimization to produce a comprehensively effective digital circuit design and its physical chip, with assistance of the Tiny Tapeout (https://tinytapeout.com/), the open source tapeout service we’ve chosen, in the facilitation of tapeout.